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general description the DS3994 is a 4-channel controller for cold-cathode fluorescent lamps (ccfls) that backlight liquid crystal displays (lcds) in tv and pc monitor applications. the DS3994? features make it suitable for use in even the largest lcds, while its low bom cost makes it ideal for the entire range of lcd tvs and monitors. the DS3994 can stagger the lamp bursts from each of the four channels. this feature allows scanning back- light schemes for video quality improvement to be implemented using a single ccfl controller ic, making it very simple and inexpensive to provide this enhance- ment. in addition, staggering the bursts from each channel can be used to minimize current ripple on the display power supply, which is especially important for larger lcds. the relative stagger between each of the channels is programmable, so this feature can be tai- lored to the specific application. the DS3994 uses a push-pull drive architecture but it can also support full and half bridge drive schemes. contact the factory for more details. applications lcd televisions lcd pc monitors features high-density ccfl controller for lcd tv and pc monitor backlights programmable staggered start for burst dimming on each channel strike frequency boost option programmable strike time can be easily cascaded minimal external components analog brightness control gate driver phasing minimizes dc supply current surges per-channel lamp fault monitoring for lamp open, lamp overcurrent, failure to strike, and overvoltage conditions accurate (?%) on-board oscillator lamp frequency (20khz to 80khz) wide range on-board dpwm burst-dimming oscillator (22.5hz to 440hz) can be synchronized to external sources for the lamp and dpwm frequencies < 10% to 100% dimming range soft-start minimizes audible transformer noise i 2 c-compatible serial port and on-board nonvolatile (nv) memory allow device customization 3-byte nv user memory for storage of serial numbers and date codes 4.5v to 5.5v single-supply operation -40? to +85? temperature range 28-pin so (300 mils) package DS3994 4-channel cold-cathode fluorescent lamp controller ______________________________________________ maxim integrated products 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsync fault scl sda ovd4 lcm4 gnd gb4 ga4 ovd3 lcm3 gb3 ga3 v cc ovd2 lcm2 gb2 ga2 ovd1 lcm1 gb1 ga1 svm bright posc psync a0 losc so-300 top view DS3994 pin configurations rev 0; 10/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information typical operating circuits appear at end of data sheet. part temp range pin-package DS3994z+ -40 c to +85 c 28 so-300 + denotes lead-free package. 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller 2 _____________________________________________________________________ absolute maximum ratings recommended operating conditions (t a = -40 c to +85 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v cc , sda, and scl relative to ground.............................................-0.5v to +6.0v voltage range on leads other than v cc , sda, and scl ..-0.5v to (v cc + 0.5v), not to exceed +6.0v operating temperature range ...........................-40 c to +85 c eeprom programming temperature range .........0 c to +70 c storage temperature range .............................-55 c to +125 c soldering temperature...................see j-std-020 specification parameter symbol conditions min typ max units supply voltage v cc (note 1) 4.5 5.5 v input logic 1 v ih 2.2 v cc + 0.3 v input logic 0 v il -0.3 0.8 v svm voltage range v svm -0.3 v cc + 0.3 v bright voltage range v bright -0.3 v cc + 0.3 v lcm voltage range v lcm (note 2) -0.3 v cc + 0.3 v ovd voltage range v ovd (note 2) -0.3 v cc + 0.3 v gate-driver output charge loading q g 20 nc electrical characteristics (v cc = +4.5v to +5.5v, t a = -40 c to +85 c.) parameter symbol conditions min typ max units supply current i cc g a , g b loaded with 600pf, 4 channels active 916ma input leakage (digital pins) i l -1.0 +1.0 a output leakage (sda, fault )i lo high impedance -1.0 +1.0 a v ol1 i ol1 = 3ma 0.4 low-level output voltage (sda, fault ) v ol2 i ol2 = 6ma 0.6 v low-level output voltage (psync, lsync) v ol3 i ol3 = 4ma 0.4 v low-level output voltage (ga, gb) v ol4 i ol4 = 4ma 0.4 v high-level output voltage (psync, lsync) v oh1 i oh1 = -1ma v cc - 0.4 v 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller _____________________________________________________________________ 3 electrical characteristics (continued) (v cc = +4.5v to +5.5v, t a = -40 c to +85 c.) parameter symbol conditions min typ max units high-level output voltage (ga, gb) v oh2 i oh2 = -1ma v cc - 0.4 v uvlo threshold v cc rising v uvlor 4.3 v uvlo threshold v cc falling v uvlof 3.7 v uvlo hysteresis v uvloh 100 mv svm falling edge threshold v svmt 1.95 2.0 2.05 v svm hysteresis v svmh 150 mv lcm and ovd source current 4a lcm and ovd sink current 4a lcm and ovd dc bias voltage v dcb 1.35 v lcm and ovd input resistance r dcb 50 k ? lamp off threshold v lot (note 3) 1.65 1.75 1.85 v lamp overcurrent threshold v loc (note 3) 3.15 3.35 3.55 v lamp regulation threshold v lrt (note 3) 2.29 2.35 2.41 v ovd threshold v ovdt (note 3) 2.25 2.35 2.45 v lamp frequency range f lf:osc 20 80 khz lamp frequency source frequency tolerance f lfs:tol losc resistor 0.1% over temperature -2 +2 % lamp frequency receiver duty cycle f lfr:duty 40 60 % dpwm frequency range f d:osc 22.5 440.0 hz dpwm source frequency tolerance f dsr:tol posc resistor 0.1% over temperature -2 +2 % dpwm receiver duty cycle f dfe:duty 40 60 % dpwm receiver frequency range f dr:osc 22.5 440.0 hz dpwm receiver minimum pulse width t dr:min (note 4) 25 s bright voltage minimum brightness v bmin positive slope (cr2.7 = 0) 0.5 v bright voltage maximum brightness v bmax positive slope (cr2.7 = 0) 2.0 v bright voltage minimum brightness v bmin positive slope (cr2.7 = 1) 0 v bright voltage maximum brightness v bmax positive slope (cr2.7 = 1) 3.3 v gate-driver output rise/fall time t r /t f c l = 600pf 50 100 ns gan and gbn duty cycle (note 5) 44 % 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller 4 _____________________________________________________________________ i 2 c ac electrical characteristics (see figure 10) (v cc = +4.5v to +5.5v, timing referenced to v il(max) and v ih(min) , t a = -40 c to +85 c.) note 1: all voltages are referenced to ground, unless otherwise noted. currents into the ic are positive, out of the ic negative. note 2: during fault conditions, the ac-coupled feedback values are allowed to be outside the absolute maximum rating of the lcm or ovd pin for up to 1 second. note 3: voltage including the dc offset, v dcb . note 4: this is the minimum pulse width guaranteed to generate an output burst, which will generate the DS3994 s minimum burst duty cycle. this duty cycle may be greater than the duty cycle of the psync input. once the duty cycle of the psync input is greater than the DS3994 s minimum duty cycle, the output s duty cycle will track the psync s duty cycle. leaving psync low (0% duty cycle) disables the gan and gbn outputs in dpwm slave mode. note 5: this is the maximum lamp frequency duty cycle that will be generated at any of the gan or gbn outputs. note 6: i 2 c interface timing shown is for fast-mode (400khz) operation. this device is also backward compatible with i 2 c stan- dard-mode timing. note 7: after this period, the first clock pulse can be generated. note 8: c b total capacitance allowed on one bus line in picofarads. note 9: eeprom write begins after a stop condition occurs. note 10: guaranteed by design. parameter symbol conditions min typ max units scl clock frequency f scl (note 6) 0 400 khz bus free time between stop and start conditions t buf 1.3 s hold time (repeated) start condition t hd:sta (note 7) 0.6 s low period of scl t low 1.3 s high period of scl t high 0.6 s data hold time t hd:dat 0 0.9 s data setup time t su:dat 100 ns start setup time t su:sta 0.6 s sda and scl rise time t r (note 8) 20 + 0.1c b 300 ns sda and scl fall time t f (note 8) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 s sda and scl capacitive loading c b (note 8) 400 pf eeprom write time t w (note 9) 20 30 ms nonvolatile memory characteristics (v cc = +4.5v to +5.5v) parameter symbol conditions min typ max units eeprom write cycles +70 c (note 10) 50,000 cycles 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller _____________________________________________________________________ 5 active supply current vs. supply voltage DS3994 toc01 supply voltage (v) supply current (ma) 5.3 5.1 4.9 4.7 6 7 8 9 10 5 4.5 5.5 4 dpwm = 10% dpwm = 50% dpwm = 100% gate q c = 3.5nc svm < 2v f lf:osc = 64khz active supply current vs. temperature DS3994 toc02 temperature ( c) supply current (ma) 22.5 6.5 7.0 7.5 8.0 9.0 8.5 9.5 10.0 10.5 11.0 6.0 -40.0 85.0 v cc = 5.5v v cc = 5.0v dpwm = 100% f lf:osc = 64khz gate q c = 3.5nc v cc = 4.5v internal frequency change vs. temperature DS3994 toc03 temperature ( c) frequency change (%) 22.5 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 -0.6 -0.8 -1.0 -40.0 85.0 lamp frequency dpwm frequency typical operation at 12v DS3994 toc04 10 s 5.0v g a 10 s 5.0v g b 10 s 2.0v lcm 10 s 2.0v ovd burst dimming at 150hz and 10% DS3994 toc08 1ms 5.0v g a 1ms 5.0v g b 1ms 2.0v lcm 1ms 2.0v ovd typical operation at 15v DS3994 toc05 10 s 5.0v g a 10 s 5.0v g b 10 s 2.0v lcm 10 s 2.0v ovd typical operation at 18v DS3994 toc06 10 s 5.0v g a 10 s 5.0v g b 10 s 2.0v lcm 10 s 2.0v ovd typical startup with svm DS3994 toc07 5ms 2.0v svm 5ms 5.0v g b 5ms 2.0v lcm 5ms 1.0v ovd typical operating characteristics (v cc = +5.0v, t a = +25 c, unless otherwise noted.) 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller 6 _____________________________________________________________________ typical operating characteristics (continued) (v cc = +5.0v, t a = +25 c, unless otherwise noted.) burst dimming at 150hz and 50% DS3994 toc09 1ms 5.0v g a 1ms 5.0v g b 1ms 2.0v lcm 1ms 1.0v ovd soft-start at v inv = 18v DS3994 toc10 20 s 5.0v g a 20 s 5.0v g b 20 s 2.0v lcm 20 s 1.0v ovd lamp strike?xpanded view DS3994 toc11 1ms 5.0v g a 1ms 5.0v g b 1ms 2.0v lcm 1ms 2.0v ovd lamp strike with open lamp autoretry disabled DS3994 toc12 0.55 5.0v g a 0.55 5.0v g b 0.55 2.0v lcm 0.55 1.0v ovd lst0 and lst1 = 0 burst dimming stagger DS3994 toc13 2.0ms 5.0v ga 1 2.0ms 5.0v ga 2 2.0ms 5.0v ga 3 2.0ms 5.0v ga 4 lamp out (lamp opened), autoretry disabled DS3994 toc14 0.1s 5.0v g a 0.1s 5.0v g b 0.1s 2.00v lcm 0.1s 2.00v ovd lamp opened lamp strike with 0% frequency boost DS3994 toc15 2ms 5.0v g a 2ms 2.0v lcm 2ms 0.5v ovd lamp strike with 33% frequency boost DS3994 toc16 2ms 5.0v g a 2ms 2.0v lcm 2ms 0.5v ovd 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller _____________________________________________________________________ 7 pin description pins by channel (n = 1 4) function name ch 1 ch 2 ch 3 ch 4 gan 7 11 17 21 mosfet a gate drive. connect directly to logic-level mode n-channel mosfet. leave open if channel is unused. gbn 8 12 18 22 mosfet b gate drive. connect directly to logic-level mode n-channel mosfet. leave open if channel is unused. lcmn 9131923 lamp current monitor input. lamp current is monitored by measuring a voltage across a resistor placed in series with the low-voltage side of the lamp. leave open if channel is unused. ovdn 10 14 20 24 overvoltage detection. lamp voltage is monitored through a capacitor- divider placed on the high-voltage side of the transformer. leave open if channel is unused. name pin function gnd 15 ground connection v cc 16 power-supply connection bright 5 analog brightness control input. used to control dpwm dimming. ground when using a pwm signal at psync to control brightness. svm 6 supply voltage monitor input. used to monitor the inverter voltage for undervoltage conditions. sda 25 se r ia l d a t a i n p u t /o u t p u t . i 2 c b i d i r ecti onal d ata p i n, w hi ch r eq ui r es a p ul l up r esi stor to r eal i ze hi g h l og i c l evel s. scl 26 serial clock input. i 2 c clock input. fault 27 fault output. this active-low, open-drain pin, requires an external pullup resistor to realize high logic levels. lsync 28 lamp frequency input/output. this pin is the input for an externally sourced lamp frequency when the DS3994 is configured as a lamp frequency receiver. if the DS3994 is configured as a lamp frequency source (i.e., the lamp frequency is generated internally), the frequency is output on this pin for use by other lamp frequency receiver DS3994s. losc 1 lamp oscillator resistor adjust. a resistor to ground on this pin sets the frequency of the lamp oscillator. a0 2 address select input. determines the DS3994 s i 2 c slave address. psync 3 dpwm input/output. this pin is the input for an externally generated dpwm signal when the DS3994 is configured as a dpwm receiver. if the DS3994 is configured as a dpwm source (i.e., the dpwm signal is generated internally), the dpwm signal is output on this pin for use by other dpwm receiver DS3994s. posc 4 dpwm oscillator resistor adjust. a resistor to ground on this lead sets the frequency of the dpwm oscillator (dimming clock). this lead can optionally accept a 22.5hz to 440hz clock as the source timing for the internal dpwm signal. 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller 8 _____________________________________________________________________ functional diagram i 2 c- compatible interface 3-byte user memory eeprom system enable/por four independent ccfl controllers channel fault channel enable [20khz to 80khz] 4-phase generator x512 pll 0 1 1 0 0 1 mux rgso bit at cr1.4 ramp generator mux poscs bit at cr1.1 mux dpss bit at cr1.3 dpwm signal gnd gbn gan mosfet gate drivers ovdn overvoltage detection lcmn lamp current monitor fault handling 20khz to 80khz sda i 2 c device configuration port lamp frequency input/output external resistor lamp frequency set dpwm signal input/output analog brightness control external resistor dpwm frequency set/ dpwm clock input scl a0 fault lsync losc psync bright posc [10.24mhz to 40.96mhz] 22.5hz to 440hz 20khz to 80khz oscillator ( 2%) 22.5hz to 440hz oscillator ( 5%) lfss bit at cr1.2 dpss bit at cr1.3 uvlo v cc [4.5v to 5.5v] svm supply voltage monitor 2.0v control registers DS3994 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller _____________________________________________________________________ 9 gate drivers mosfet gate drivers gan gbn digital ccfl controller channel fault 512 x lamp frequency [10.24mhz ~ 40.96mhz] lamp frequency [20khz ~ 80khz] dimming pwm signal channel enable 1.0v lcmn lamp current monitor 400mv 2.0v lamp overcurrent lamp strike and regulation loc bit in cr1.0 lamp out 1.0v ovdn overvoltage detector lamp maximum voltage regulation 64 lamp cycle integrator overvoltage figure 1. per channel logic diagram detailed description the DS3994 uses a push-pull drive scheme to convert a dc voltage (5v to 24v) to the high-voltage (600v rms to 1200v rms ) ac waveform that is required to power the ccfls. the push-pull drive scheme uses a minimal number of external components, which reduces assembly cost and makes the printed circuit board design easy to implement. the push-pull drive scheme also provides an efficient dc-to-ac conversion and produces near-sinusoidal waveforms. each DS3994 channel drives two logic-level n-channel mosfets that are connected between the ends of a step-up transformer and ground (see figure 1 and the typical operating circuit ). the transformer has a center tap on the primary side that is connected to a dc voltage supply. the DS3994 alternately turns on the two mosfets to create the high-voltage ac waveform on the secondary side. by varying the duration of the mosfet turn-on times, the controller is able to accurately control the amount of current flowing through the ccfl. a resistor in series with the ccfl s ground connection enables current monitoring. the voltage across this resistor is fed to the lamp current monitor (lcm) input on the DS3994. the DS3994 compares the peak resistor voltage against an internal reference voltage to deter- mine the duty cycle for the mosfet gates. each ccfl receives independent current monitoring and control, which results in equal brightness across all of the lamps and maximizes the lamp s brightness and lifetime. the DS3994 can also drive more than one lamp per channel. see the typical operating circuit section for implementation details when using multiple lamps per channel. eeprom registers and i 2 c-compatible serial interface the DS3994 uses an i 2 c-compatible serial interface for communication with the on-board eeprom configuration registers and user memory. the configuration registers, four burst dimming stagger registers (bds1/2/3/4), and three control registers (cr1/2/3) allow the user to cus- tomize many DS3994 parameters such as the time delay to stagger the burst dimming between channels, the lamp and dimming frequency sources, fault-monitoring options, and channel enabling/disabling. the three bytes of nonvolatile user memory can be used to store manu- facturing data such as date codes, serial numbers, or product identification numbers. the device is shipped from the factory with the con- figuration registers programmed to a set of default configuration parameters. to inquire about custom factory programming, please send an email to mixedsignal.apps@dalsemi.com. 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller 10 ____________________________________________________________________ channel phasing the lamp-frequency mosfet gate turn-on times are equally phased among the four channels during the burst period. this reduces the inrush current that would result from all lamps switching simultaneously, and hence eases the design requirements for the dc supply. figure 2 details how the four channels are phased. note that it is the lamp frequency signals that are phased, not the dpwm signals. see the burst dimming stagger functionality section for details or to adjust the dpwm signals of each channel. lamp dimming control (dpwm) the DS3994 uses a digital pulse-width modulated (dpwm) signal (22.5hz to 440hz) to provide efficient and precise lamp dimming. during the high period of the dpwm cycle, the lamps are driven at the selected lamp frequency (20khz to 80khz) as shown in figure 7. this part of the cycle is called the burst period because of the lamp frequency burst that occurs dur- ing this time. during the low period of the dpwm cycle, the controller disables the mosfet gate drivers so the lamps are not driven. this causes the current to stop flowing in the lamps, but the time is short enough to keep the lamps from de-ionizing. dimming is increased/ decreased by adjusting (i.e., modulating) the duty cycle of the dpwm signal. the DS3994 can generate its own dpwm signal internally (set dpss = 0 in cr1), which can then be sourced to other DS3994s if required, or the dpwm signal can be supplied from an external source (set dpss = 1 in cr1). variable mosfet gate duty cycle 12 3 41 2 341 2 3 4 4 ga1 channel sequence gb1 ga2 gb2 ga3 gb3 ga4 gb4 mosfet gate- drive signals at lamp frequency dimming clock (dpwm) frequency figure 2. channel phasing detail 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller ______________________________________________________________________________________________________ 11 to generate the dpwm signal internally, the DS3994 requires a clock (referred to as the dimming clock) to set the dpwm frequency. the user can supply the dim- ming clock by setting poscs = 1 in cr1 and applying an external 22.5hz to 440hz signal at the posc pin, or DS3994 s clock can be generated by the DS3994 s oscillator (set poscs = 0 in cr1), in which case the frequency is set by an external resistor at the posc pin. these two dimming clock options are shown in figure 3. regardless of whether the dimming clock is generated internally or sourced externally, the poscr1 and poscr2 bits in cr2 must be set to match the desired dimming clock frequency. lamp dimming control (dpwm) when the dpwm signal is generated internally, its duty cycle (and, thus, the lamp brightness) is controlled by a user-applied analog voltage at the bright input. users can select a positive or negative slope for the bright pin s dimming input as well as the voltage range. if slope = 0 in cr3, then the slope is positive. this means that a bright voltage less than the minimum voltage causes the DS3994 to operate with the minimum burst duty cycle, providing the lowest brightness set- ting, while any voltage greater than the maximum volt- age causes a 100% burst duty cycle (i.e., lamps always being driven), which provides the maximum brightness. for voltages between the minimum voltage and the maximum voltage, the duty cycle varies linearly between the minimum and 100%. the internally generated dpwm signal is available at the psync i/o pin (set rgso = 0 in cr1) for sourcing to other DS3994s, if any, in the circuit. this allows all DS3994s in the system to be synchronized to the same dpwm signal. the DS3994 that is generating the dpwm signal for other DS3994s in the system is referred to as the dpwm source. bright psync (output) posc 0.5v or 0.0v 2.0v or 3.3v 22.5hz to 440hz resistor to set the dimming frequency dpwm signal analog dimming control voltage resistor-set dimming clock bright psync (output) posc 22.5hz to 440hz 22.5hz to 440hz dpwm signal external dimming clock analog dimming control voltage external dimming clock 0.5v or 0.0v 2.0v or 3.3v figure 3. dpwm source configuration options bright psync (input) posc 22.5hz to 440hz dpwm signal figure 4. dpwm receiver configuration table 1. bright analog dimming input slope and voltage range configuration cr2.7 cr3.0 range slope minimum brightness maximum brightness 0 0 0.5 to 2v positive 0.5v 2.0v 0 1 0.5 to 2v negative 2.0v 0.5v 1 0 0 to 3.3v positive 0v 3.3v 1 1 0 to 3.3v negative 3.3v 0v 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller 12 ____________________________________________________________________ when the dpwm signal is provided by an external source, either from the psync pin of another DS3994 or from some other user-generated source, it is input into the psync i/o pin of the DS3994. in this mode, the bright and posc inputs are disabled and should be grounded (see figure 4). when multiple DS3994s are used in a design, DS3994s configured to use externally generated dpwm signals are referred to as dpwm receivers. burst dimming stagger (bds) functionality the DS3994 also features burst dimming stagger (bds) functionality integrated into the burst dimming con- troller. bds is useful to reduce the current ripple on the dc supply as well as improve the visual motion response of the lcd panel. this feature allows users to enter a digital code into each channel independent register (bds1/2/3/4) that would delay the start of each burst peri od. the 8-bit bds code can be calculated by using table 2 and the following equations. m, lamp cycle period multiplication factor poscr1 (cr2.2) poscr0 (cr2.1) selected pwm oscillator range (hz) lamp oscillator = 40 to 80khz (lofs = 0) lamp oscillator = 20 to 40khz (lofs = 1) 0 0 22.5 to 55 8 8 0 1 45 to 110 4 4 1 0 90 to 220 2 2 1 1 180 to 440 1 1 table 2. multiplication factor m, based on lamp frequency oscillator and dpwm frequency oscillator if a bds_delay is used that is longer than the burst peri- od, then the gate drivers, ga and gb, have no output. for example, assume a lamp frequency of 50khz and a burst frequency of 167hz. the step resolution of the burst-dimming stagger would be 40s (2/50,000). to achieve equal stagger, as shown in figure 5, the bds1/2/3/4 registers would be programmed as described in table 3. bds_delay = bds_resolution x bds_8-bit_value bds_resolution f lf : osc = m channel 1 burst dimming cycle (167hz/6ms) channel 2 channel 3 channel 4 1.5ms 3.0ms 4.5ms figure 5. example burst dimming stagger cycle channel register desired stagger (ms) step resolution (?) count programmed value 1 bds1 0 40 0 00h 2 bds2 1.5 40 38 26h 3 bds3 3.0 40 75 48h 4 bds4 4.5 40 113 71h table 3. example bds1/2/3/4 programmed values 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller ____________________________________________________________________ 13 lamp strike frequency boost the DS3994 also features a programmable lamp strike frequency boost option. during the strike period, the transformer secondary is essentially unloaded. the lamp frequency be can be easily increased causing a higher strike voltage. the sb0/1/2 bits in cr3 control how the frequency is increased during lamp strike. a setting of 000b results in no frequency increase, while the maximum setting (111b) causes a 100% increase. once the DS3994 detects that the lamp has struck, the lamp frequency is automatically reset to the nominal run level. lamp frequency configuration the DS3994 can generate its own lamp frequency clock internally (set lfss = 0 in cr1), which can then be sourced to other DS3994s if required, or the lamp clock can be supplied from an external source (set lfss = 1 in cr1). when the lamp clock is internally generated, the frequency (20khz to 80khz) is set by an external resistor at the losc. in this case, the DS3994 can act as a lamp frequency source because the lamp clock is output at the lsync i/o pin for synchronizing any other DS3994s configured as lamp frequency receivers. the DS3994 acts as a lamp frequency receiver when the lamp clock is supplied externally. in this case, a 20khz to 80khz clock must be supplied at the lsync i/o. the external clock can originate from the lsync i/o of a DS3994 configured as a lamp frequency source or from some other source. the lofs bit in cr3 must be set to match the appropri- ate lamp frequency range. if a 20khz to 40khz frequen- cy is used, then lofs must be set to 1; if a 40khz to 80khz frequency is used, then lofs must be set to 0. configuring systems with multiple DS3994s the source and receiver options for the lamp frequency clock and dpwm signal allow multiple DS3994s to be synchronized in systems requiring more than four lamps. the lamp and dimming clocks can either be generated on board the DS3994 using external resis- tors to set the frequency, or they can be sourced by the host system to synchronize the DS3994 to other system resources. figure 6 shows various multiple DS3994 configurations that allow both lamp and/or dpwm syn- chronization for all DS3994s in the system. dpwm soft-start at the beginning of each lamp burst, the DS3994 pro- vides a soft-start that slowly increases the mosfet gate-driver duty cycle (see figure 7). this minimizes the possibility of audible transformer noise that could result from current surges in the transformer primary. the soft-start length is fixed at 16 lamp cycles. 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller 14 ____________________________________________________________________ bright lamp frequency source dpwm source psync lsync posc losc resistor-set dimming frequency resistor-set lamp frequency DS3994 bright lamp frequency receiver dpwm receiver psync lsync posc losc DS3994 bright lamp frequency source dpwm source psync lsync posc losc analog brightness analog brightness resistor-set lamp frequency dimming clock (22.5hz to 440hz) dpwm signal (22.5hz to 440hz) DS3994 bright lamp frequency receiver dpwm receiver psync lsync posc losc DS3994 bright lamp frequency source dpwm receiver psync lsync posc losc resistor-set lamp frequency DS3994 bright lamp frequency receiver dpwm receiver psync lsync posc losc DS3994 bright lamp frequency receiver dpwm source psync lsync posc losc resistor-set dimming frequency DS3994 bright lamp frequency receiver dpwm receiver psync lsync posc losc DS3994 bright lamp frequency receiver dpwm source psync lsync posc losc analog brightness analog brightness lamp clock (20khz to 80khz) dimming clock (22.5hz to 440hz) lamp clock (20khz to 80khz) dpwm signal (22.5hz to 440hz) lamp clock (20khz to 80khz) DS3994 bright lamp frequency receiver dpwm receiver psync lsync posc losc DS3994 bright lamp frequency receiver dpwm receiver psync lsync posc losc DS3994 bright lamp frequency receiver dpwm receiver psync lsync posc losc DS3994 0.5v or 0.0v 2.0v or 3.3v 0.5v or 0.0v 2.0v or 3.3v 0.5v or 0.0v 2.0v or 3.3v 0.5v or 0.0v 2.0v or 3.3v figure 6. frequency configuration options for designs using multiple DS3994s 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller ____________________________________________________________________ 15 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 lamp current soft-start soft-start (expanded) 22.5hz to 440hz dpwm signal lamp current lamp cycle gan/gbn mosfet gate drivers soft-start profile with increasing mosfet pulse widths over a 16 lamp cycle period results in a linear ramp in lamp current. 1 figure 7. digital pwm dimming and soft-start 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller 16 ____________________________________________________________________ setting the lamp and dimming clock (dpwm) frequencies using external resistors both the lamp and dimming clock frequencies can be set using external resistors. the resistance required for either frequency can be determined using the following formula: where k = 1600k ?? khz for lamp frequency calculations. when calculating the resistor value for the dimming clock frequency, k will be one of four values as determined by the desired frequency and the poscr0 and poscr1 bit settings as shown in the control register 2 (cr2) in the detailed register descriptions section. example: selecting the resistor values to configure a DS3994 to have a 50khz lamp frequency and a 160hz dimming clock frequency: for this configuration, poscr0 and poscr1 must be programmed to 1 and 0, respectively, to select 90hz to 220hz as the dimming clock frequency range. this sets k for the dimming clock resistor (r posc ) calculation to 4k ?? khz. for the lamp frequency resistor (r losc ) cal- culation, k = 1600k ?? khz, which allows the lamp fre- quency k value regardless of the frequency. the formula above can now be used to calculate the resis- tor values for r losc and r posc as follows: supply monitoring the DS3994 monitors both the transformer s dc supply and its own v cc supply to ensure that both voltage lev- els are adequate for proper operation. the inverter s transformer supply (v inv ) is monitored using an external resistor-divider that is the input into a comparator (see figure 8) with a 2v threshold. using the equation below to determine the resistor values, the supply voltage monitor (svm) trip point (v trip ) can be customized to shut off the inverter when the trans- former s input voltage drops below any specified value. operating with the transformer s supply at too low of a level can prevent the inverter from reaching the strike voltage and could potentially cause numerous other problems. proper use of the svm can prevent these problems. if desired, the svm can be disabled by con- necting the svm pin to v cc . the v cc monitor is used as a 5v supply undervoltage lockout (uvlo) that prevents operation when the DS3994 does not have adequate voltage for its analog circuitry to operate or to drive the external mosfets. the v cc moni- tor features hysteresis to prevent v cc noise from causing spurious operation when v cc is near the trip point. this monitor cannot be disabled by any means. fault monitoring the DS3994 provides extensive fault monitoring for each channel. it can detect open-lamp, lamp overcur- rent, failure to strike, and overvoltage conditions. the DS3994 can be configured to disable all channels if one or more channels enter a fault state, or it can be configured to disable only the channel where the fault occurred. once a fault state has been entered, the fault output is asserted and the channel(s) remain disabled until either the DS3994 is power-cycled or the inverter s dc supply is power-cycled. the DS3994 can also be configured to automatically attempt to clear a detected fault (except lamp overcurrent) by restriking the lamp, as explained in step 4. configuration bits for the fault monitoring options are located in the control registers. v rr r trip . = + ? ? ? ? ? ? 20 12 1 r k khz khz k r k khz khz k losc posc , . . = ? = = ? = 1600 50 32 4 0 160 25 0 ? ? ? ? r k f osc osc = v inv 2.0v svm example: r 1 = 10k ? , r 2 = 40k ? sets an svm trip point of 10v. r 2 r 1 DS3994 figure 8. setting the svm threshold voltage 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller ____________________________________________________________________ 17 figure 9 shows a flowchart of how the DS3994 controls and monitors each lamp. the steps are as follows: 1) supply check the lamps will not turn on unless the DS3994 supply voltage is 4.5v and the voltage at the supply voltage monitor (svm) input is 2v. 2) strike lamp when both the DS3994 and the dc inverter supplies are above these minimum values, the DS3994 attempts to strike each enabled chan- nel. the DS3994 slowly ramps up the mosfet gate duty cycle until the lamp strikes. the controller detects that the lamp has struck by detecting cur- rent flow in the lamp. if during the strike ramp the maximum allowable voltage is reached, the con- troller stops increasing the mosfet gate duty cycle to keep from overstressing the system. the DS3994 goes into a fault handling state (step 4) if the lamp has not struck after the timeout period as defined by the lst0 and lst1 control bits in the cr3 register. if an overvoltage event is detected during the strike attempt, the DS3994 disables the mosfet gate dri- vers and goes into the fault handling state. 3) run lamp once the lamp is struck, the DS3994 moves to the run lamp stage. in the run lamp stage, the DS3994 adjusts the mosfet gate duty cycle to optimize the lamp current. the gate duty cycle is always constrained to keep the system from exceeding the maximum allowable lamp voltage. if lamp current ever drops below the lamp out ref- erence point for the period as defined by the lst0 and lst1 control bits in the cr3 register, then the lamp is considered extinguished. in this case the mosfet gate drivers are disabled and the device moves to the fault handling stage. 4) fault handling during fault handling, the DS3994 performs an optional (user-selectable) automatic retry to attempt to clear all faults except a lamp overcurrent. the automatic retry makes 14 addition- al attempts to rectify the fault before declaring the channel in a fault state and permanently disabling the channel. between each of the 14 attempts, the controller waits 1024 lamp cycles. in the case of a lamp overcurrent, the DS3994 instantaneously declares the channel to be in a fault state and per- manently disables the channel. the DS3994 can be configured to disable all channels if one or more channels enters a fault state or it can be configured to disable only the channel where the fault occurred. once a fault state is entered, the channel remains in that state until one of the following occurs: ? v cc drops below the uvlo threshold. ? the svm threshold is crossed. ? the channel is disabled. 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller 18 ____________________________________________________________________ mosfet gate drivers enabled device and inverter supplies at proper levels? strike lamp [ramp and regulate to ovd threshold] fault wait [1024 lamp cycles] lamp strike timeout [see register cr3] run lamp [regulate lamp current bounded by lamp voltage] lamp out timeout [see register cr3] increment fault counter fault counter = 15? lamp overcurrent [instantaneous if enabled via the loc bit at cr1.0] no yes auto retry enabled? [ard bit at cr1.5] no yes yes overvoltage [64 lamp cycles] if lamp regulation threshold is met reset fault counter and fault output fault state [activate fault output] figure 9. fault-handling flow chart 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller ____________________________________________________________________ 19 byte address byte name factory default* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f0h reserved 21h f1h reserved 43h f2h reserved 65h f3h reserved 77h f4h cr1 20h dpd frs ard rgso dpss lfss poscs loc f5h cr2 08h bvrs ld1 ld0 0 1 poscr1 poscr0 umwp f6h reserved 00h f7h reserved 00h f8h bds1 00h burst dimming stagger for channel 1. f9h bds2 00h burst dimming stagger for channel 2. fah bds3 00h burst dimming stagger for channel 3. fbh bds4 00h burst dimming stagger for channel 4. fch cr3 00h lofs igo sb2 sb1 sb0 lst1 lst0 slope fd-ffh user memory 00h ee ee ee ee ee ee ee ee * this is the factory-programmed default stored in eeprom. table 4. register map detailed register descriptions the DS3994 s register map is shown in table 4. detailed register and bit descriptions follow in the sub- sequent tables. 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller 20 ____________________________________________________________________ f4h: control register 1 (cr1) bit name function 0 loc lamp overcurrent 0 = lamp overcurrent detection disabled. 1 = lamp overcurrent detection enabled. 1 poscs posc select. see poscr0 and poscr1 bits in control register 2 to select the oscillator range. 0 = connect posc to ground with a resistor to set the dimming frequency. 1 = connect posc to an external 22.5hz to 440hz dimming clock to set the dimming frequency. 2 lfss lamp frequency source select 0 = lamp frequency source mode. the lamp frequency is generated internally and sourced at the lsync output for use by lamp frequency receivers. 1 = lamp frequency receiver mode. the lamp frequency must be provided at the lsync input. 3 dpss dpwm signal source select 0 = d p w m sour ce m od e. d p wm si g nal i s g ener ated i nter nal l y, and can b e outp ut at p s y n c p i n ( see rgs o b i t) . 1 = dpwm receiver mode. dpwm signal is generated externally and supplied at the psync input. 4 rgso ramp generator source option 0 = sources dpwm at the psync output. 1 = sources the internal ramp generator at psync output. 5 ard autoretry disable 0 = autoretry function enabled. 1 = autoretry function disabled. 6 frs fault response select 0 = disable only the malfunctioning channel. 1 = disable all channels upon fault detection at any channel. 7 dpd dpwm disable 0 = dpwm function enabled. 1 = dpwm function disabled. dpwm set to 100% duty cycle. 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller ____________________________________________________________________ 21 f5h: control register 2 (cr2) bit name function 0 umwp user memory write protect 0 = user memory write access blocked 1 = user memory write access permitted 1 poscr0 dpwm oscillator range select. when using an external source for the dimming clock, these bits must be set to match the external oscillator s frequency. when using a resistor to set the dimming frequency, these bits plus the external resistor control the frequency. poscr1 poscr0 dimming clock (dpwm) frequency range (hz) k (k ? -khz) 0 0 22.5 to 55.0 1 0 1 45 to 110 2 1 0 90 to 220 4 2 poscr1 1 1 180 to 440 8 3 reserved reserved. should be set to one. 4 reserved reserved. should be set to zero. lamp disable. used to disable channels if all 4 are not required for an application. ld1 ld0 channels disabled number of active lamp channels 0 0 all channels enabled 4 5 ld0 014 3 1 0 2/4 2 6 ld1 1 1 1/2/4 1 7 bvrs bright voltage range select. 0 = 0.5v to 2.0v 1 = 0.0v to 3.3v f8 fbh: burst dimming stagger (bds1/2/3/4) bit name function 0 bdsc0 1 bdsc1 2 bdsc2 3 bdsc3 4 bdsc4 5 bdsc5 6 bdsc6 7 bdsc7 8-bit programmable counter that staggers the start of burst dimming. 00h = 0ms stagger. setting the stagger longer than the burst dimming cycle results in the channel never turning on. see table 2. 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller 22 ____________________________________________________________________ fch: control register 3 (cr3) bit name function 0 slope bright analog dimming slope select 0 = positive slope 1 = negative slope strike and lamp out timeout in lamp frequency cycles lst1 lst0 lamp oscillator = 40khz to 80khz (lofs = 0) lamp oscillator = 20khz to 40khz (lofs = 1) example time out if lamp frequency is 25khz or 50khz 0 0 32,768 16,384 0.66 seconds 1 lst0 0 1 65,536 32,768 1.31 seconds 1 0 98,304 49,152 1.97 seconds 2 lst1 1 1 131,072 65,536 2.62 seconds note: the strike frequency boost does not affect this timeout. lamp strike frequency boost select sb2 sb1 sb0 lamp strike frequency boost example strike frequency if lamp frequency is 50khz 3 sb0 0 0 0 0% 50khz 0 0 1 14% 57khz 0 1 0 23% 61.5khz 0 1 1 33% 66.7khz 4 sb1 1 0 0 46% 73khz 1 0 1 60% 80khz 1 1 0 78% 89khz 5 sb2 1 1 1 100% 100khz 6igo invert mosfet gate a and gate b driver outputs 0 = do not invert ga and gb outputs. 1 = invert ga and gb outputs. 7 lofs lamp oscillator frequency select 0 = 40khz to 80khz 1 = 20khz to 40khz 4 .com datasheet u
i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses, start, and stop conditions. slave devices: slave devices send and receive data at the master s request. bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and in their logic-high states. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see the timing dia- gram for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high gener- ates a stop condition. see the timing diagram for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identically to a nor- mal start condition. see the timing diagram for applica- ble timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements (see figure 10). data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time (see figure 10) before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master gener- ates all scl clock pulses including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowl- edgement (ack) or not acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the 9th bit. a device per- forms a nack by transmitting a one during the 9th bit. timing (figure 10) for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. DS3994 4-channel cold-cathode fluorescent lamp controller ____________________________________________________________________ 23 figure 10. i 2 c timing diagram sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop note: timing is referenced to v il(max) and v ih(min) . start 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller 24 ____________________________________________________________________ byte write: a byte write consists of 8 bits of informa- tion transferred from the master to the slave (most sig- nificant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the mas- ter are done according to the bit-write definition and the acknowledgement is read using the bit-read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to terminate communication so the slave will return control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave addressing byte sent immediately following a start condition. the slave address byte (figure 11) contains the slave address in the most signifi- cant seven bits and the r/ w bit in the least significant bit. the DS3994 s slave address is 101000a 0 (binary), where a 0 is the value of the address pin (a 0 ). the address pin allows the device to respond to one of two possible slave addresses. by writing the correct slave address with r/ w = 0, the master writes data to the slave. if r/ w = 1, the master reads data from the slave. if an incorrect slave address is written, the DS3994 will assume the master is communicating with another i 2 c device and ignore the communications until the next start condition is sent. memory address: during an i 2 c write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte trans- mitted during a write operation following the slave address byte. i 2 c communication writing a data byte to a slave: the master must gen- erate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. remember the master must read the slave s acknowledgement during all byte write operations. see figure 12 for more detail. acknowledge polling: any time eeprom is written, the DS3994 requires the eeprom write time (t w ) after the stop condition to write the contents to eeprom. during the eeprom write time, the DS3994 will not acknowledge its slave address because it is busy. it is possible to take advantage of that phenomenon by repeatedly addressing the DS3994, which allows the next byte of data to be written as soon as the DS3994 is ready to receive the data. the alternative to acknowl- edge polling is to wait for a maximum period of t w to elapse before attempting to write again to the DS3994. eeprom write cycles: the number of times the DS3994 s eeprom can be written before it fails is specified in the nonvolatile memory characteristics table. this specification is shown at the worst-case write temperature. the DS3994 is typically capable of handling many additional write cycles when the writes are performed at room temperature. reading a data byte from a slave: to read a single byte from the slave the master generates a start condi- tion, writes the slave address byte with r/ w = 0, writes the memory address, generates a repeated start condi- tion, writes the slave address with r/ w = 1, reads the data byte with a nack to indicate the end of the trans- fer, and generates a stop condition. see figure 12 for more detail. figure 11. DS3994? slave address byte 7-bit slave address most significant bit a 0 pin value determines read or write r/w 1 01 0 00 a 0 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller ____________________________________________________________________ 25 figure 12. i 2 c communications examples xxxxxxxx 101 0 a 0 0 0 0 communications key write a single byte 8-bits address or data white boxes indicate the master is controlling sda notes 2) the first byte sent after a start condition is always the slave address followed by the read/write bit. shaded boxes indicate the slave is controlling sda start ack not ack s sa a a p data memory address 101 0 a 0 0 0 0 101 0 a 0 1 0 0 read a single byte sa asr an p data memory address a pn sr stop repeated start 1) all bytes are sent most significant bit first. applications information addressing multiple DS3994s on a common i 2 c bus each DS3994 responds to one of two possible slave addresses based on the state of the address input (a 0 ). for information about device addressing see the i 2 c communications section. power-supply decoupling to achieve best results, it is recommended that each v cc pin is decoupled with a 0.01f or a 0.1f capacitor to gnd. use high-quality, ceramic, surface-mount capac- itors, and mount the capacitors as close as possible to the v cc and gnd pins to minimize trace inductance. setting the rms lamp current resistor r8 in the typical operating circuit (figure 13) sets the lamp current. r8 = 140 ? corresponds to a 5ma rms lamp current as long as the current waveform is approximately sinusoidal. the formula to determine the resistor value for a given sinusoidal lamp current is: component selection external component selection has a large impact on the overall system performance and cost. the two most important external components are the transformers and n-channel mosfets. the transformer should be able to operate in the 20khz to 80khz frequency range of the DS3994, and the turns ratio should be selected so the mosfet drivers run at 28% to 35% duty cycle during steady state operation. the transformer must be able to withstand the high open-circuit voltage that will be used to strike the lamp. additionally, its primary/secondary resistance and inductance characteristics must be considered because they contribute significantly to determining the efficiency and transient response of the system. table 5 shows a transformer specification that has been utilized for a 12v inverter supply, 438mm x 2.2mm lamp design. the n-channel mosfet must have a threshold voltage that is low enough to work with logic-level signals, a low on-resistance to maximize efficiency and limit the n- channel mosfet s power dissipation, and a break- down voltage high enough to handle the transient. the breakdown voltage should be a minimum of 3x the inverter voltage supply. additionally, the total gate charge must be less than q g , which is specified in the recommended dc operating conditions table. these specifications are easily met by many of the dual n- channel mosfets now available in so-8 packages. table 6 lists suggested values for the external resistors and capacitors used in the typical operating circuit. r i lamp rms 8 1 2 () = 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller 26 ____________________________________________________________________ table 5. transformer specifications parameter conditions min typ max units turns ratio (secondary/primary) (notes 1, 2, 3) 40 frequency 40 80 khz output power 6w output current 58ma primary dcr center tap to one end 200 m ? secondary dcr 500 ? primary leakage 12 h secondary leakage 185 mh primary inductance 70 h secondary inductance 500 mh center tap voltage 10.8 12 13.2 v 100ms minimum 2000 secondary output voltage continuous 1000 v rms table 6. resistor and capacitor selection guide designator qty value tolerance (%) at 25 c temperature coefficient notes r1 1 10k ? 1 r2 1 12.5k ? to 105k ? 1 see the setting the svm threshold voltage section. r3 1 20k ? to 40k ? 1 153ppm/ c 2% or less total tolerance. see the lamp frequency configuration section to determine value. r4 1 18k ? to 45k ? 1 153ppm/ c 2% or less total tolerance. see the lamp frequency configuration section to determine value. r5 1 4.7k ? 5 any grade r6 1 4.7k ? 5 any grade r7 1 4.7k ? 5 any grade r8 1/ch 140 ? 1 see the setting the rms lamp current section. c1 1/ch 100nf 10 x7r c ap aci tor val ue w i l l al so affect lc m b i as vol tag e d ur i ng p ow er - up . a l ar g er cap aci tor m ay cause a l ong er ti m e for v d c b to r each i ts nor m al op er ati ng l evel . c2 1/ch 10pf 5 1000ppm/ c 2kv to 4kv breakdown voltage required. c3 1/ch 27nf 5 x7r c ap aci tor val ue w i l l al so affect lc m b i as vol tag e d ur i ng p ow er - up . a l ar g er cap aci tor m ay cause a l ong er ti m e for v d c b to r each i ts nor m al op er ati ng l evel . c4 1/ch 33f 20 any grade c5 1 0.1f 10 x7r place close to v cc and gnd on DS3994. note 1: primary should be bifilar wound with center tap connection. note 2: turns ratio is defined as secondary winding divided by the sum of both primary windings. note 3: 40:1 is the nominal turns ratio for driving a 438mm x 2.2mm lamp with a 12v supply. refer to application note 3375 for more information. 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller ____________________________________________________________________ 27 typical operating circuits DS3994 bright v cc v cc svm gan gbn ovdn lcmn c1 lamp voltage monitor c3 r8 ccfl lamp transformer dual power mosfet supply voltage (5v 10% to 24v 10%) v cc = 5v 10% c2 r1 r2 c5 c4 lamp current monitor note 1: only one channel shown to simplify drawing. note 2: see the component selection section for recommended external components. gnd psync lsync losc posc r3 r4 r5 r6 r7 configuration port fault sda scl a0 analog brightness external digital pwm input/ internal digital pwm output external lamp frequency input/ internal lamp frequency output figure 13. typical operating circuit 4 .com datasheet u
DS3994 4-channel cold-cathode fluorescent lamp controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 28 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation. heaney package information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo . chip information transistor count: 53,000 substrate connected to ground typical operating circuits (continued) DS3994 bright v cc ga gb ovd lcm 1 of 4 channels c l r fb +12v to +24v lm339 +5v dual n-channel power mosfet device supply voltage (5v 10%) inverter supply voltage (12v 10% to 24v 10%) bulk power supply capacitance c h ccfl lamp a r1 r2 gnd psync lsync losc posc r3 r4 4.7k ? 4.7k ? configuration port fault sda scl svm a0 analog brightness on = open off/reset = closed dpwm signal input/output lamp frequency input/output c l r fb c h c l r fb c h c l r fb c h ccfl lamp b ccfl lamp c ccfl lamp d figure 14. typical operating circuit with multiple lamps per channel 4 .com datasheet u

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